1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to the structure of a clamping circuit for limiting the amplitude of a signal on an input or output signal line coupled to a pad. More specifically, the present invention relates to a circuit for clamping an overshoot voltage and/or an undershoot voltage applied to the pad.
2. Description of the Prior Art
As the operating speed of a semiconductor integrated circuit is increased, the speed for transmitting a signal between such integrated circuits is also increased. In particular, the rise/fall time tr/tf of a digital signal changing between a high level and a low level is reduced when the signal transmission speed is increased. A signal line of a printed circuit board on which the semiconductor integrated circuit is mounted has parasitic inductance and parasitic capacitance. When a signal having a short rise/fall time tr/tf is transmitted, therefore, the current change ratio di/dt is increased to increase an overshoot/undershoot voltage of the signal on the line on the printed circuit board. Following this overshoot/undershoot, oscillation of the signal is caused on an LC circuit formed by the parasitic inductance and the parasitic capacitance, to result in ringing. When the overshoot/undershoot voltage increases and the amplitude of this ringing increases to exceed the input logical threshold of an input stage of a next stage circuit or a receiving circuit, a false signal is generated to cause spurious switching of the next stage circuit or the receiving circuit, resulting in a circuit malfunction. Further, the state of the signal cannot be determined until the ringing is stabilized, and hence high-speed signal transmission cannot be implemented.
When electrons are injected into a substrate region of a dynamic random access memory (DRAM) by a large overshoot/undershoot voltage and the injected electrons are stored in a storage node storing information of a memory cell, the data stored in the memory cell disappears to cause a soft error. When the potential of the substrate region changes, further, the threshold voltage of an insulated gate field effect transistor (MOS transistor) of a component of DRAM changes responsively to cause deviation in operation timing and to reduce an operation margin.
FIG. 33 schematically illustrates the arrangement of a plurality of integrated circuits mounted on a printed circuit board. Referring to FIG. 33, integrated circuits 100a to 100n, such as memory LSIs, are coupled in common to a transmission line 102 transmitting a signal. The transmission line 102 is connected with the integrated circuits 100a to 100n through branch lines 107a to 107n at branch points 106a to 106n respectively. The transmission line 102 is provided with a driver circuit 104 for transmitting a signal from a processor or a logic circuit (not shown).
In the system shown in FIG. 33, ringing on the transmission line 102 must be suppressed by matching the output impedance of the driver circuit 104 with the characteristic impedance of the transmission line 102. However, the drivability of the driver circuit 104 is increased for increasing the operating speed of the system. The output impedance of the driver circuit 104 is generally reduced for increasing the drivability thereof. Thus, the output impedance of the driver circuit 104 is mismatched with the characteristic impedance of the transmission line 102, and an overshoot/undershoot is apt to be caused.
In order to suppress reflection of the signal from an end point 108, a resistive element (terminating resistance) having the same resistance value as the characteristic impedance of the transmission line 102 may be provided between the end point 108 and a voltage source (e.g., a ground node) supplying a constant voltage. When such terminating resistance is provided, however, a current flows through the resistance to increase power consumption of the whole system.
The transmission line 102 is connected to the integrated circuits 100a to 100n through the branch lines 107a to 107n at the branch points 106a to 106n respectively. In each of the integrated circuits 100a to 100n, each of the branch lines 107a to 107n is connected to a gate electrode of an input MOS transistor (if the integrated circuit is a MOS integrated circuit). The gate electrode of the MOS transistor, which is isolated from a source/drain by a gate insulation film, has high resistance against an input signal. In other words, the integrated circuits 100a to 100n have high input impedances to the branch lines 107a to 107n. This state is equivalent to open states of the branch lines 107a to 107n as viewed from the branch points 106a to 106n, and input parts of the integrated circuits 100a to 100n reflect the signal transmitted from the branch points 106a to 106n, to readily cause an overshoot/undershoot on the signal on the transmission line 102.
Influence by such an overshoot/undershoot and subsequent ringing remarkably increases particularly when the amplitude of the signal transmitted through the transmission line 102 is reduced. In order to suppress such an overshoot/undershoot of the signal, a clamping circuit employing a diode element may be provided on each of the integrated circuits 100a to 100n for suppressing an overshoot/undershoot voltage.
FIG. 34 illustrates an exemplary structure of a conventional clamping circuit provided on an input part of an integrated circuit. Referring to FIG. 34, a diode element 113 is connected between an internal input line 111 connected to a bonding pad 110 and a power supply node 112, and another diode element 115 is connected between the input line 111 and a ground node 114. A resistor 116 for current limitation is provided between the input line 111 and an invertor 117 which is an internal circuit. The pad 110 is connected to an external terminal through a bonding wire. The diode element 113 is connected in the forward direction from the signal input line 111 to the power supply node 112, and the diode element 115 is connected in the reverse direction from the input line 111 to the ground node 114.
When a voltage lower than the ground voltage is applied to the input line 111 through the pad 110, the diode element 115 is rendered conductive to supply a current from the ground node 114 to the input line 111 for clamping the undershoot voltage at the ground voltage level. When an overshoot voltage higher than a power supply voltage Vcc is applied to the input line 111 through the pad 110, the diode element 113 is rendered conductive to clamp the overshoot voltage at the level of the power supply voltage Vcc.
Thus, the clamping circuit clamps the overshoot/undershoot voltage on the input line 111, for preventing the invertor 117 of an internal circuit from malfunctioning while preventing the internal circuit 117 from being suffered from electrostatic breakdown due to application of a large electrostatic voltage to the pad 110 with the resistor 116.
Each of the diode elements 113 and 114 has a built-in voltage (contact potential) across a P-N junction and is rendered conductive when a voltage larger than the built-in voltage is applied in the forward direction. In general, this voltage is referred to as a forward voltage drop Vf. As shown in FIG. 35, therefore, an overshoot voltage of a signal IN on the input line 111 is clamped at a voltage Vcc+Vf while an undershoot voltage is clamped at a voltage Vss-Vf (=-0.7 V). This state is implemented when the diode element 113 or 115 ideally responds at a high speed for clamping the overshoot/undershoot voltage. In practice, however, the absolute value of the clamping voltage for the input signal IN on the input line 111 is greater than that of the ideal clamping voltage due to a delay in response resulting from switching characteristics of the diode element 113 or 115. When the power supply voltage Vcc is at a low level of 2.0 or 2.5 V, the value of the forward voltage drop Vf cannot be neglected and the reliability of the internal circuit (invertor) 117 cannot be sufficiently guaranteed.
When a waveform exceeding the input logical threshold voltage of the internal circuit (invertor) 117 is present on ringing following such an overshoot/undershoot, the invertor 117 performs a switching operation and an internal signal is unstabilized. Particularly when the power supply voltage Vcc lowers, the amplitude of the ringing relatively increases to cause spurious switching of the internal circuit (invertor) 117 and the internal signal from the internal circuit (invertor) 117 is unstabilized to increase the possibility of a malfunction.
The problem of the overshoot/undershoot on the input line 111 similarly takes place also where the pad 110 is an output pad. When an output buffer of the integrated circuit outputs a signal at a high speed, an output signal line is charged/discharged at a high speed. In this case, an overshoot/undershoot is similarly caused on the signal due to presence of large parasitic inductance and parasitic capacitance on the pad, a bonding wire, an external pin terminal and such. In this case, a signal having an overshoot/undershoot is transmitted through the transmission line 102 receiving a data signal from the integrated circuit, to result in a malfunction in a receiving circuit. Further, the receiving circuit cannot produce an internal signal until the signal is defined, and hence high-speed signal transfer cannot be performed.
When employing a diode element as a clamping element, the built-in voltage of a P-N junction part thereof has temperature dependency that the built-in voltage reduces as the temperature rises. When driving the semiconductor integrated circuit in a low temperature region, therefore, the absolute value of the clamping level increases, the internal circuit cannot be sufficiently protected, and the signal amplitude cannot be sufficiently suppressed.